A Programmable Logic Device (PLD) is a user-configurable logic device that performs a function on input data so as to produce desired output data. The PLD is configured (programmed) by applying a series of voltage pulses to memory cells within the device. There are many types of PLDs, each optimized to perform a specific logic function within given performance parameters.
One type of PLD, known as a Programmable Read-Only Memory (PROM), became available in the early 1970s. The primary uses of PROMs have been in memory-type applications, such as display look-up tables, and software storage known as firmware. Referring now to FIG. 1, PROMs comprise programmable OR array 11 fed by a fixed AND array 12. The AND array is fully decoded, meaning that all possible combinations of the inputs I.sub.0 . . . I.sub.2 have a unique product term. As a result of the full decoding scheme, which results in 2.sup.n product terms, where n is the number of inputs, PROMs are typically relatively large and costly devices. In addition, PROM devices tend to be slower than other PLDs, due to the switching time of the large arrays. Only some small PROMs operate fast enough to be useful as logic elements.
In the mid 1970s, a new type of PLD, known as the Field Programmable Logic Array (FPLA), was devised. Referring now to FIG. 2, it will be noted that an FPLA has a basic structure similar to that of a PROM. However, both its AND array 21 and OR array 22 are programmable. The fact that the AND array is not dully decoded results in a device that is smaller, faster and better able to handle logic functions than PROMs. FPLAs are extensively used in applications where output functions are very similar, allowing full utilization of the shared product terms. Although FPLAs were initially considered somewhat slow and costly, new technology is changing that perception.
In the late 1970s, another type of PLD, known as the Programmable Array Logic (PAL) device, debuted. Referring now to FIG. 3, it will be noted that the basic structure is shared with PROMs and FPLAs. However, this time, the AND array 31 is programmable and the OR array 32 is fixed. The quantity of product terms per output is fixed by the hardwired OR array. Compared to PROMs and FPLAs, PALs offer improved performance and more efficient architecture for most logic functions.
In FIG. 4, a conventional method of implementing the programmable AND terms in either a PAL or an FPLA. For simplicity, the nonvolatile devices are depicted as pairs of simple switches, which either connect or disconnect an associated product term or its complement through the appropriate N-channel transistor. It should also be noted that, in this disclosure, the complement of a digital signal value is denoted by the signal value followed by an asterisk. For example, the complement of I is I*. In the example of FIG. 4, the logical operation of X=I.sub.0 I.sub.1 *I.sub.2 is implemented by programming switches SW0B, SW1A and SW2B as closed, and switches SW0A, SW1B and SW2A as open. When inputs I.sub.0 and I.sub.2 are high, and input I.sub.1 is low, node X1 will be pulled high by the current source I.sub.s, and the output X will be high; for other input values, X will be low. This method of constructing AND arrays has inherent disadvantages. Unless transition detection circuits are added to the inputs, power is consumed during static states whenever the product term in not matched (i.e., the inputs are other than high, low, and high, respectively). With transition detection on the inputs, zero power drain is achieved except when inputs are toggled. Otherwise, the current source I.sub.s is turned off a short time after the inputs are toggled and after the output X has latched. The current source I.sub.s is turned back on whenever any of the inputs are retoggled. Although the addition of transition detection circuitry achieves a substantially zero power device, device performance is compromised with a reduction in speed. Typical PALs having no transition detection circuitry have access times on the order of 10-20 nanoseconds, and power dissipation greater than 100 mA. With the addition of transition detection circuitry, zero power dissipation is achieved for static states, but with a rise in access time to around 25 nanoseconds.
What is needed is a high-speed, zero power logic cell which may be used to construct both PALs or FPLAs.